Noise isolation and the elimination of complementary metal-oxide semiconductors (CMOS) latchup are significant issues in advanced CMOS technology, radio frequency (RF) CMOS, and bipolar CMOS (BiCMOS) Silicon Germanium (SiGe) technology. Latchup conditions typically occur within peripheral circuits or internal circuits, within one circuit (intra-circuit), or between multiple circuits (inter-circuit). In one such example, latchup occurs when a PNPN structure transitions from a low-current/high-voltage state to a high-current/low-voltage state through a negative resistance region (i.e., forming an S-Type I-V (current/voltage) characteristic).
In particular, latchup is known to be initiated by an equivalent circuit of a cross-coupled PNP and NPN transistor. With the base and collector regions being cross-coupled, current flows from one device leading to the initiation of the second device (“regenerative feedback”). These PNP and NPN elements can be any diffusions or implanted regions of other circuit elements (e.g., p-channel MOSFETs, n-channel MOSFETs, resistors, etc.) or actual PNP and NPN bipolar transistors. In CMOS structures, the PNPN structure can be formed with a p-diffusion in an n-well, and a n-diffusion in a p-substrate (“parasitic PNPN”). In this case, the well and substrate regions are inherently involved in the latchup current exchange between regions in the device.
The condition for triggering a latchup is a function of the current gain of the PNP and NPN transistors, and the resistance between the emitter and the base regions. This inherently involves the well and substrate regions. The likelihood or sensitivity of a particular PNPN structure to latchup is a function of a same combination of spacing (e.g., base width of the NPN and base width of the PNP), current gain of the transistors, substrate resistance and spacings, the well resistance and spacings, and isolation regions.
Latchup can also occur as a result of the interaction of an electrostatic discharge (ESD) device, the input/output (I/O) off-chip driver and adjacent circuitry initiated in the substrate from the overshoot and undershoot phenomena. These factors can be generated by CMOS off-chip driver (OCD) circuitry, receiver networks, and ESD devices. In CMOS I/O circuitry, undershoot and overshoot can lead to injection in the substrate, and simultaneous switching of circuitry where overshoot or undershoot injection occurs may lead to both noise injection and latchup conditions. Also, supporting elements in these circuits, such as pass transistors, resistor elements, test functions, over voltage dielectric limiting circuitry, bleed resistors, keeper networks and other elements can be present, contributing to noise injection into the substrate and latchup.
With the scaling of standard CMOS technology, the spacing of the p+/n+ space decreases, leading to a lower trigger condition and the onset of CMOS latchup. With the scaling of the shallow trench isolation (STI) for aspect ratio, the vulnerability of CMOS technology to latchup has increased. Vertical scaling of the wells, and lower n-well and p-well implant doses also has increased the lateral parasitic bipolar current gains, leading to lower latchup robustness.
With the transition from p+ substrates to low doped p-substrates, the latchup robustness has continued to decrease. Also, the effectiveness of n-wells as guard ring structures may reduce internal and external latchup problems. But, with mixed signal applications and radio frequency (RF) chips, a higher concern for noise reduction has lead to the continued lowering of the substrate doping concentration. This continues to lead to lower latchup immunity in mixed signal applications and RF technologies.
Latchup also can occur from voltage or current pulses that occur on the power supply lines. Transient pulses on power rails (e.g., substrate or wells) can trigger latchup processes. Latchup can also occur from a stimulus to the well or substrate external to the region of a thyristor structure from minority carriers.
Latchup can be initiated from internal or external stimulus, and is known to occur from single event upsets (SEU), which can include terrestrial emissions from nuclear processes, and cosmic ray events, as well as events in space environments. Cosmic ray particles can include proton, neutron, and gamma events, as well as a number of particles that enter the earth atmosphere. Terrestrial emissions from radioactive events, such as alpha particles, and other radioactive decay emissions can also lead to latchup in semiconductors.
For military, surveillance, satellite, and other outer space applications, it is desirable to have a high tolerance to latchup. Latchup can lead to failure of space applications triggered by cosmic rays, heavy ions, proton and neutron events. The higher the latchup margin in military and outer space applications, the higher the vulnerability to single even upset (SEU) initiated latchup.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.